1. Field of the Invention
The present invention relates to a display control system of a personal computer, and more particularly to a display control system with two display modes of a graphics mode and a text mode.
2. Description of the Related Art
Generally, a display controller of a personal computer has two display modes: a graphics mode and a text mode. The graphics mode is a mode in which image data stored in an image memory is displayed on a display monitor of a computer. The text mode is a mode in which character fonts are displayed on the display monitor according to the arrangement of character codes in the image memory. In both of the graphics and text modes, the data read from the image memory is converted into a video signal by a display control circuit in the display controller and then is supplied to the display monitor. In this case, the display control circuit operates in synchronization with a video clock. The video clock is a synchronizing signal used to supply a video signal in dots to the display monitor. The frequency of the video clock is determined by the display timing of the display monitor.
Accessing the image memory is controlled by a memory control circuit in the display controller. The accesses of the memory control circuit to the image memory include accesses for the CPU to draw pictures and those for reading the data from the image memory to refresh the screen.
The higher the resolution of the display screen becomes, the larger the amount of data that must be read from the image memory. Particularly, in the case of graphics data, the number of bits per dot is large, so that it takes a lot of time to read the data from the image memory.
In this case, since the time that the image memory is occupied to refresh the screen becomes longer, this limits the time that the CPU can use the image memory to rewrite the data in the image memory. This is the main cause of a deterioration in the drawing performance of the CPU.
Accordingly, to improve the speed at which data is read from the image memory in the graphics mode, recent display controllers use a page-mode read cycle and a memory clock for memory control only.
The page-mode read cycle is a serial access mode in which a plurality of data items stored consecutively at row addresses in the image memory are read out consecutively. Use of this mode enables a large number of graphics data items to be read from the image memory at high speed.
Since the frequency of the memory clock can be determined only by the performance of the image memory independently of the frequency of the video clock, the former can be set higher than the latter. Therefore, using the memory clock to drive the memory control circuit enables the graphics data to be read from the image memory at higher speed.
Consequently, use of the page-mode read cycle and the memory clock shortens the time that the image memory is occupied to refresh the screen in the graphics mode, so that the CPU can spend so much longer time in drawing pictures.
With conventional display controllers, however, serial access to the image memory using such a page-mode memory cycle and a memory clock is effected regardless of whether the graphics mode or the text mode is active.
This accessing technique has the disadvantage of increasing the reading speed in the graphics mode, but decreasing it in the text mode to the contrary.
Hereinafter, referring to FIGS. 1 and 2, an image memory access operation will be described which uses a page-mode read cycle and a memory clock in the text mode.
FIG. 1 conceptually shows the configuration of the memory control circuit which provides access control of the image memory. FIG. 2 is a timing chart illustrating access timing of the image memory.
In the text mode, among four maps (MPA0 to MAP3) constituting the image memory 50, MAP0, MAP1, and MAP2 are used, and MAP3 is not used. MAP0 stores character codes (Code), MAP1 stores attributes (ATT), and MAP3 stores character fonts (Font).
When the text data is displayed on a display monitor, MAP0 and MAP1 in the image memory 50 first undergo serial access in a page-mode read cycle. In the page-mode read cycle, a plurality of column addresses CA are generated consecutively for a single row address RA and then supplied to MAP0 and MAP1. Then, character codes are read consecutively from MAP0 and attributes are read consecutively from MAP1. These character codes and attributes are written into an FIFO buffer 57 one after another.
Once the FIFO buffer 57 gets full, the character codes and attributes are read from the FIFO buffer 57 and then latched in latch circuits 59, 60, respectively. The latched character code is used as a font address for accessing MAP2.
Then, a single read cycle using the font address is executed, and row address RA and column address CA corresponding to the font address are supplied to MAP2. Thus, MAP2 is random-accessed in a single read cycle, with the result that as much font data as one raster of the character font pattern specified at the font address is read out. This font data is latched in a latch circuit 61. With the same timing, the attribute in the latch circuit 60 is transferred to a latch circuit 62 and then latched there. Thereafter, according to the font data and attribute, video data is generated dot by dot.
As explained above, in the text mode, accessing MAP0 and MAP1 must be effected in a page-mode read cycle and thereafter, MAP2 must be accessed in a single read cycle. The single read cycle is repeated as many times as the number of character codes consecutively read in the page-mode read cycle. Therefore, the larger the number of character codes read in the page-mode read cycle becomes, the longer the execution period of the single read cycle lasts.
During the execution period of a single read cycle for MAP2, a page-mode read cycle for MAP0 and MAP1 cannot be executed. The reason for this is that since each page-mode read cycle is relatively long, it is impossible to insert a page-mode cycle into a vacant time in the single read cycle.
Consequently, in the text mode, using a page-mode read cycle makes the time very long for which only MAP2 is being accessed in a single read cycle. This therefore results in a decrease in the data reading speed.
Since a conventional image memory is subjected to serial access regardless of whether the display mode is the text mode or the graphics mode, a random access must be repeated many times to read character fonts after a page-mode read cycle has been executed to read the character code and attribute. In this case, the next page-mode read cycle is not executed until the reading of the character fonts corresponding to all the character codes read in the page-mode read cycle has been completed. This introduces the disadvantage that the time for which the image memory is occupied for data reading becomes longer, and consequently the time for which the CPU provides control of the image memory becomes shorter.